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<div class="header">
  <div class="headertitle"><div class="title">TIM Extended Remapping <div class="ingroups"><a class="el" href="group___s_t_m32_h7xx___h_a_l___driver.html">STM32H7xx_HAL_Driver</a> &raquo; <a class="el" href="group___t_i_m_ex.html">TIMEx</a> &raquo; <a class="el" href="group___t_i_m_ex___exported___constants.html">TIM Extended Exported Constants</a></div></div></div>
</div><!--header-->
<div class="contents">
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-define-members" class="groupheader"><a id="define-members" name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga5156e463b51b1a7d92e6d87c2be4563a" id="r_ga5156e463b51b1a7d92e6d87c2be4563a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga5156e463b51b1a7d92e6d87c2be4563a">TIM_TIM1_ETR_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:ga2e3eb3f4f99db6c14b3ce91bebfe8d07" id="r_ga2e3eb3f4f99db6c14b3ce91bebfe8d07"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga2e3eb3f4f99db6c14b3ce91bebfe8d07">TIM_TIM1_ETR_COMP1</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga1e5c447a1de2571985f74ca5ee201c56">TIM1_AF1_ETRSEL_0</a></td></tr>
<tr class="memitem:ga734d16e8c8e368bedc159f97422e26b9" id="r_ga734d16e8c8e368bedc159f97422e26b9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga734d16e8c8e368bedc159f97422e26b9">TIM_TIM1_ETR_COMP2</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga269809ebc603562522c733f7b518bcc3">TIM1_AF1_ETRSEL_1</a></td></tr>
<tr class="memitem:gaa5a7accd83b70cbaf790bd26fd8e4538" id="r_gaa5a7accd83b70cbaf790bd26fd8e4538"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaa5a7accd83b70cbaf790bd26fd8e4538">TIM_TIM1_ETR_ADC1_AWD1</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga269809ebc603562522c733f7b518bcc3">TIM1_AF1_ETRSEL_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e5c447a1de2571985f74ca5ee201c56">TIM1_AF1_ETRSEL_0</a>)</td></tr>
<tr class="memitem:ga4ee5007933efeaae07c745062ffc2776" id="r_ga4ee5007933efeaae07c745062ffc2776"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga4ee5007933efeaae07c745062ffc2776">TIM_TIM1_ETR_ADC1_AWD2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga891aa4abfb026ec12d7e78366c57861c">TIM1_AF1_ETRSEL_2</a>)</td></tr>
<tr class="memitem:ga6a448a71300d1f8f81e6eb0dcc31f15a" id="r_ga6a448a71300d1f8f81e6eb0dcc31f15a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga6a448a71300d1f8f81e6eb0dcc31f15a">TIM_TIM1_ETR_ADC1_AWD3</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga891aa4abfb026ec12d7e78366c57861c">TIM1_AF1_ETRSEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e5c447a1de2571985f74ca5ee201c56">TIM1_AF1_ETRSEL_0</a>)</td></tr>
<tr class="memitem:ga95a93aa08f9c8b8d58dd6e30e30f41c1" id="r_ga95a93aa08f9c8b8d58dd6e30e30f41c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga95a93aa08f9c8b8d58dd6e30e30f41c1">TIM_TIM1_ETR_ADC3_AWD1</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga891aa4abfb026ec12d7e78366c57861c">TIM1_AF1_ETRSEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga269809ebc603562522c733f7b518bcc3">TIM1_AF1_ETRSEL_1</a>)</td></tr>
<tr class="memitem:gad3cbe27b5e94414e39b52843054a4cee" id="r_gad3cbe27b5e94414e39b52843054a4cee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gad3cbe27b5e94414e39b52843054a4cee">TIM_TIM1_ETR_ADC3_AWD2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga891aa4abfb026ec12d7e78366c57861c">TIM1_AF1_ETRSEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga269809ebc603562522c733f7b518bcc3">TIM1_AF1_ETRSEL_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e5c447a1de2571985f74ca5ee201c56">TIM1_AF1_ETRSEL_0</a>)</td></tr>
<tr class="memitem:gaf0be1d196c76f0d45c4f41d61d4af0f6" id="r_gaf0be1d196c76f0d45c4f41d61d4af0f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaf0be1d196c76f0d45c4f41d61d4af0f6">TIM_TIM1_ETR_ADC3_AWD3</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga4b00c39efe4c62ef0c7391da38f4d93e">TIM1_AF1_ETRSEL_3</a></td></tr>
<tr class="memitem:gabcec3c5e9dad306b68d34e5b9257a281" id="r_gabcec3c5e9dad306b68d34e5b9257a281"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gabcec3c5e9dad306b68d34e5b9257a281">TIM_TIM8_ETR_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:gadcbcb76d19c2ccb5ae46fdc7e7d88f8b" id="r_gadcbcb76d19c2ccb5ae46fdc7e7d88f8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gadcbcb76d19c2ccb5ae46fdc7e7d88f8b">TIM_TIM8_ETR_COMP1</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff3eda56bcb98d020fa1b1573c4f912">TIM8_AF1_ETRSEL_0</a></td></tr>
<tr class="memitem:gae93f8a76facb81f8d962bb7c88dc25f0" id="r_gae93f8a76facb81f8d962bb7c88dc25f0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gae93f8a76facb81f8d962bb7c88dc25f0">TIM_TIM8_ETR_COMP2</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga8115191f924a8817c45e04078725f242">TIM8_AF1_ETRSEL_1</a></td></tr>
<tr class="memitem:ga7a832c5903108f2a06208c58585f7579" id="r_ga7a832c5903108f2a06208c58585f7579"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga7a832c5903108f2a06208c58585f7579">TIM_TIM8_ETR_ADC2_AWD1</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8115191f924a8817c45e04078725f242">TIM8_AF1_ETRSEL_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff3eda56bcb98d020fa1b1573c4f912">TIM8_AF1_ETRSEL_0</a>)</td></tr>
<tr class="memitem:gae0c7be84fda65b37b00a8896b98775c3" id="r_gae0c7be84fda65b37b00a8896b98775c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gae0c7be84fda65b37b00a8896b98775c3">TIM_TIM8_ETR_ADC2_AWD2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga7dc91956b73a05f0ab3465a124e27e97">TIM8_AF1_ETRSEL_2</a>)</td></tr>
<tr class="memitem:ga02c57d201dbc0416eed0e333a6347b5b" id="r_ga02c57d201dbc0416eed0e333a6347b5b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga02c57d201dbc0416eed0e333a6347b5b">TIM_TIM8_ETR_ADC2_AWD3</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga7dc91956b73a05f0ab3465a124e27e97">TIM8_AF1_ETRSEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff3eda56bcb98d020fa1b1573c4f912">TIM8_AF1_ETRSEL_0</a>)</td></tr>
<tr class="memitem:ga7cb16632bf98d6961d21172aa42373e3" id="r_ga7cb16632bf98d6961d21172aa42373e3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga7cb16632bf98d6961d21172aa42373e3">TIM_TIM8_ETR_ADC3_AWD1</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga7dc91956b73a05f0ab3465a124e27e97">TIM8_AF1_ETRSEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga8115191f924a8817c45e04078725f242">TIM8_AF1_ETRSEL_1</a>)</td></tr>
<tr class="memitem:ga84b90475edbe94a4cdbef6f5f602ac9b" id="r_ga84b90475edbe94a4cdbef6f5f602ac9b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga84b90475edbe94a4cdbef6f5f602ac9b">TIM_TIM8_ETR_ADC3_AWD2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga7dc91956b73a05f0ab3465a124e27e97">TIM8_AF1_ETRSEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga8115191f924a8817c45e04078725f242">TIM8_AF1_ETRSEL_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff3eda56bcb98d020fa1b1573c4f912">TIM8_AF1_ETRSEL_0</a>)</td></tr>
<tr class="memitem:ga8f39897f883d4efa8357d1ba28bc100b" id="r_ga8f39897f883d4efa8357d1ba28bc100b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga8f39897f883d4efa8357d1ba28bc100b">TIM_TIM8_ETR_ADC3_AWD3</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga97fe71b195c1bbc5175e3db42d09c062">TIM8_AF1_ETRSEL_3</a></td></tr>
<tr class="memitem:ga05e1c800a3f8e7eb60b50f446cf321f7" id="r_ga05e1c800a3f8e7eb60b50f446cf321f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga05e1c800a3f8e7eb60b50f446cf321f7">TIM_TIM2_ETR_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:ga79a125bc7559dc01f8de056e19f11972" id="r_ga79a125bc7559dc01f8de056e19f11972"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga79a125bc7559dc01f8de056e19f11972">TIM_TIM2_ETR_COMP1</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gaaa7a4ed17a8432d8c81e31e32dd87e20">TIM2_AF1_ETRSEL_0</a>)</td></tr>
<tr class="memitem:ga76dfe019f143b4bff5ba2c2e1a38a387" id="r_ga76dfe019f143b4bff5ba2c2e1a38a387"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga76dfe019f143b4bff5ba2c2e1a38a387">TIM_TIM2_ETR_COMP2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga6a1413b9834ebc2b96c8eb27b74b0fdc">TIM2_AF1_ETRSEL_1</a>)</td></tr>
<tr class="memitem:gae69141882323f8b603da7a0343995dca" id="r_gae69141882323f8b603da7a0343995dca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gae69141882323f8b603da7a0343995dca">TIM_TIM2_ETR_RCC_LSE</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga6a1413b9834ebc2b96c8eb27b74b0fdc">TIM2_AF1_ETRSEL_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff3eda56bcb98d020fa1b1573c4f912">TIM8_AF1_ETRSEL_0</a>)</td></tr>
<tr class="memitem:ga901919d24f481b3ca744ff06cd98bdb8" id="r_ga901919d24f481b3ca744ff06cd98bdb8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga901919d24f481b3ca744ff06cd98bdb8">TIM_TIM2_ETR_SAI1_FSA</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga38cf3fbfe20afba58f315ace95c88016">TIM2_AF1_ETRSEL_2</a></td></tr>
<tr class="memitem:gab369084ac6b74b818f48995770cf2221" id="r_gab369084ac6b74b818f48995770cf2221"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gab369084ac6b74b818f48995770cf2221">TIM_TIM2_ETR_SAI1_FSB</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga38cf3fbfe20afba58f315ace95c88016">TIM2_AF1_ETRSEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff3eda56bcb98d020fa1b1573c4f912">TIM8_AF1_ETRSEL_0</a>)</td></tr>
<tr class="memitem:gad86579b249d2c04a99c8412a8c72af97" id="r_gad86579b249d2c04a99c8412a8c72af97"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gad86579b249d2c04a99c8412a8c72af97">TIM_TIM3_ETR_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:gaea6cbaddf4da816fd4afd13ad7953079" id="r_gaea6cbaddf4da816fd4afd13ad7953079"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaea6cbaddf4da816fd4afd13ad7953079">TIM_TIM3_ETR_COMP1</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaaf25073af3e775f18278b711d3719957">TIM3_AF1_ETRSEL_0</a></td></tr>
<tr class="memitem:ga5df745d19761f4c212140c70d4271692" id="r_ga5df745d19761f4c212140c70d4271692"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga5df745d19761f4c212140c70d4271692">TIM_TIM5_ETR_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:gaca05dbe7ce7bc979d5e30f355285a51c" id="r_gaca05dbe7ce7bc979d5e30f355285a51c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaca05dbe7ce7bc979d5e30f355285a51c">TIM_TIM5_ETR_SAI2_FSA</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gabaeb0ecb379e37e51722902144404520">TIM5_AF1_ETRSEL_0</a></td></tr>
<tr class="memitem:ga11e3c0b2d38048d8d15e8623ff61a408" id="r_ga11e3c0b2d38048d8d15e8623ff61a408"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga11e3c0b2d38048d8d15e8623ff61a408">TIM_TIM5_ETR_SAI2_FSB</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga92b38d638ecda48a0da085cfd8ce86bf">TIM5_AF1_ETRSEL_1</a></td></tr>
<tr class="memitem:gac6ad331bf73260161a6e9c3b2ee412f3" id="r_gac6ad331bf73260161a6e9c3b2ee412f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gac6ad331bf73260161a6e9c3b2ee412f3">TIM_TIM5_ETR_SAI4_FSA</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gabaeb0ecb379e37e51722902144404520">TIM5_AF1_ETRSEL_0</a></td></tr>
<tr class="memitem:ga5dd267b5ce57d4c9d0736f3da988d9d9" id="r_ga5dd267b5ce57d4c9d0736f3da988d9d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga5dd267b5ce57d4c9d0736f3da988d9d9">TIM_TIM5_ETR_SAI4_FSB</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga92b38d638ecda48a0da085cfd8ce86bf">TIM5_AF1_ETRSEL_1</a></td></tr>
<tr class="memitem:gae50809628b49070fd6720a5a28e5e175" id="r_gae50809628b49070fd6720a5a28e5e175"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gae50809628b49070fd6720a5a28e5e175">TIM_TIM23_ETR_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:ga818b9fe379711929c05c8cd61dcd45f2" id="r_ga818b9fe379711929c05c8cd61dcd45f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga818b9fe379711929c05c8cd61dcd45f2">TIM_TIM23_ETR_COMP1</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gaaa7a4ed17a8432d8c81e31e32dd87e20">TIM2_AF1_ETRSEL_0</a>)</td></tr>
<tr class="memitem:ga7365daffa2ee6ff2680a2cce2251499b" id="r_ga7365daffa2ee6ff2680a2cce2251499b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga7365daffa2ee6ff2680a2cce2251499b">TIM_TIM23_ETR_COMP2</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga6a1413b9834ebc2b96c8eb27b74b0fdc">TIM2_AF1_ETRSEL_1</a>)</td></tr>
<tr class="memitem:ga7baa5fe8462ef94cae713e4367d9d3e8" id="r_ga7baa5fe8462ef94cae713e4367d9d3e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga7baa5fe8462ef94cae713e4367d9d3e8">TIM_TIM24_ETR_GPIO</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:ga02942441fbd3f26678ff95395a09b89c" id="r_ga02942441fbd3f26678ff95395a09b89c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga02942441fbd3f26678ff95395a09b89c">TIM_TIM24_ETR_SAI4_FSA</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gabaeb0ecb379e37e51722902144404520">TIM5_AF1_ETRSEL_0</a></td></tr>
<tr class="memitem:gade1f234256056c4a8739abb2c6e35f26" id="r_gade1f234256056c4a8739abb2c6e35f26"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gade1f234256056c4a8739abb2c6e35f26">TIM_TIM24_ETR_SAI4_FSB</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga92b38d638ecda48a0da085cfd8ce86bf">TIM5_AF1_ETRSEL_1</a></td></tr>
<tr class="memitem:gab59f38eafd161977848d82893351f552" id="r_gab59f38eafd161977848d82893351f552"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gab59f38eafd161977848d82893351f552">TIM_TIM24_ETR_SAI1_FSA</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga6a1413b9834ebc2b96c8eb27b74b0fdc">TIM2_AF1_ETRSEL_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff3eda56bcb98d020fa1b1573c4f912">TIM8_AF1_ETRSEL_0</a>)</td></tr>
<tr class="memitem:ga0bf08e73da65956929e36e05e4873c42" id="r_ga0bf08e73da65956929e36e05e4873c42"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga0bf08e73da65956929e36e05e4873c42">TIM_TIM24_ETR_SAI1_FSB</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga38cf3fbfe20afba58f315ace95c88016">TIM2_AF1_ETRSEL_2</a></td></tr>
</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<a name="doc-define-members" id="doc-define-members"></a><h2 id="header-doc-define-members" class="groupheader">Macro Definition Documentation</h2>
<a id="gaa5a7accd83b70cbaf790bd26fd8e4538" name="gaa5a7accd83b70cbaf790bd26fd8e4538"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa5a7accd83b70cbaf790bd26fd8e4538">&#9670;&#160;</a></span>TIM_TIM1_ETR_ADC1_AWD1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define TIM_TIM1_ETR_ADC1_AWD1&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga269809ebc603562522c733f7b518bcc3">TIM1_AF1_ETRSEL_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e5c447a1de2571985f74ca5ee201c56">TIM1_AF1_ETRSEL_0</a>)</td>
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</div><div class="memdoc">
<p>TIM1_ETR is connected to ADC1 AWD1 </p>

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</div>
<a id="ga4ee5007933efeaae07c745062ffc2776" name="ga4ee5007933efeaae07c745062ffc2776"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4ee5007933efeaae07c745062ffc2776">&#9670;&#160;</a></span>TIM_TIM1_ETR_ADC1_AWD2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define TIM_TIM1_ETR_ADC1_AWD2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga891aa4abfb026ec12d7e78366c57861c">TIM1_AF1_ETRSEL_2</a>)</td>
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      </table>
</div><div class="memdoc">
<p>TIM1_ETR is connected to ADC1 AWD2 </p>

</div>
</div>
<a id="ga6a448a71300d1f8f81e6eb0dcc31f15a" name="ga6a448a71300d1f8f81e6eb0dcc31f15a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6a448a71300d1f8f81e6eb0dcc31f15a">&#9670;&#160;</a></span>TIM_TIM1_ETR_ADC1_AWD3</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define TIM_TIM1_ETR_ADC1_AWD3&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga891aa4abfb026ec12d7e78366c57861c">TIM1_AF1_ETRSEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e5c447a1de2571985f74ca5ee201c56">TIM1_AF1_ETRSEL_0</a>)</td>
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      </table>
</div><div class="memdoc">
<p>TIM1_ETR is connected to ADC1 AWD3 </p>

</div>
</div>
<a id="ga95a93aa08f9c8b8d58dd6e30e30f41c1" name="ga95a93aa08f9c8b8d58dd6e30e30f41c1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga95a93aa08f9c8b8d58dd6e30e30f41c1">&#9670;&#160;</a></span>TIM_TIM1_ETR_ADC3_AWD1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define TIM_TIM1_ETR_ADC3_AWD1&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga891aa4abfb026ec12d7e78366c57861c">TIM1_AF1_ETRSEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga269809ebc603562522c733f7b518bcc3">TIM1_AF1_ETRSEL_1</a>)</td>
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      </table>
</div><div class="memdoc">
<p>TIM1_ETR is connected to ADC3 AWD1 </p>

</div>
</div>
<a id="gad3cbe27b5e94414e39b52843054a4cee" name="gad3cbe27b5e94414e39b52843054a4cee"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad3cbe27b5e94414e39b52843054a4cee">&#9670;&#160;</a></span>TIM_TIM1_ETR_ADC3_AWD2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM1_ETR_ADC3_AWD2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga891aa4abfb026ec12d7e78366c57861c">TIM1_AF1_ETRSEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga269809ebc603562522c733f7b518bcc3">TIM1_AF1_ETRSEL_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga1e5c447a1de2571985f74ca5ee201c56">TIM1_AF1_ETRSEL_0</a>)</td>
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      </table>
</div><div class="memdoc">
<p>TIM1_ETR is connected to ADC3 AWD2 </p>

</div>
</div>
<a id="gaf0be1d196c76f0d45c4f41d61d4af0f6" name="gaf0be1d196c76f0d45c4f41d61d4af0f6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf0be1d196c76f0d45c4f41d61d4af0f6">&#9670;&#160;</a></span>TIM_TIM1_ETR_ADC3_AWD3</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define TIM_TIM1_ETR_ADC3_AWD3&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga4b00c39efe4c62ef0c7391da38f4d93e">TIM1_AF1_ETRSEL_3</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM1_ETR is connected to ADC3 AWD3 </p>

</div>
</div>
<a id="ga2e3eb3f4f99db6c14b3ce91bebfe8d07" name="ga2e3eb3f4f99db6c14b3ce91bebfe8d07"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga2e3eb3f4f99db6c14b3ce91bebfe8d07">&#9670;&#160;</a></span>TIM_TIM1_ETR_COMP1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM1_ETR_COMP1&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga1e5c447a1de2571985f74ca5ee201c56">TIM1_AF1_ETRSEL_0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM1_ETR is connected to COMP1 OUT </p>

</div>
</div>
<a id="ga734d16e8c8e368bedc159f97422e26b9" name="ga734d16e8c8e368bedc159f97422e26b9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga734d16e8c8e368bedc159f97422e26b9">&#9670;&#160;</a></span>TIM_TIM1_ETR_COMP2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM1_ETR_COMP2&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga269809ebc603562522c733f7b518bcc3">TIM1_AF1_ETRSEL_1</a></td>
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      </table>
</div><div class="memdoc">
<p>TIM1_ETR is connected to COMP2 OUT </p>

</div>
</div>
<a id="ga5156e463b51b1a7d92e6d87c2be4563a" name="ga5156e463b51b1a7d92e6d87c2be4563a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5156e463b51b1a7d92e6d87c2be4563a">&#9670;&#160;</a></span>TIM_TIM1_ETR_GPIO</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM1_ETR_GPIO&#160;&#160;&#160;0x00000000U</td>
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      </table>
</div><div class="memdoc">
<p>TIM1_ETR is connected to GPIO </p>

</div>
</div>
<a id="ga818b9fe379711929c05c8cd61dcd45f2" name="ga818b9fe379711929c05c8cd61dcd45f2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga818b9fe379711929c05c8cd61dcd45f2">&#9670;&#160;</a></span>TIM_TIM23_ETR_COMP1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM23_ETR_COMP1&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gaaa7a4ed17a8432d8c81e31e32dd87e20">TIM2_AF1_ETRSEL_0</a>)</td>
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      </table>
</div><div class="memdoc">
<p>TIM23_ETR is connected to COMP1 OUT </p>

</div>
</div>
<a id="ga7365daffa2ee6ff2680a2cce2251499b" name="ga7365daffa2ee6ff2680a2cce2251499b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7365daffa2ee6ff2680a2cce2251499b">&#9670;&#160;</a></span>TIM_TIM23_ETR_COMP2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM23_ETR_COMP2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga6a1413b9834ebc2b96c8eb27b74b0fdc">TIM2_AF1_ETRSEL_1</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM23_ETR is connected to COMP2 OUT </p>

</div>
</div>
<a id="gae50809628b49070fd6720a5a28e5e175" name="gae50809628b49070fd6720a5a28e5e175"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae50809628b49070fd6720a5a28e5e175">&#9670;&#160;</a></span>TIM_TIM23_ETR_GPIO</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM23_ETR_GPIO&#160;&#160;&#160;0x00000000U</td>
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      </table>
</div><div class="memdoc">
<p>TIM23_ETR is connected to GPIO </p>

</div>
</div>
<a id="ga7baa5fe8462ef94cae713e4367d9d3e8" name="ga7baa5fe8462ef94cae713e4367d9d3e8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7baa5fe8462ef94cae713e4367d9d3e8">&#9670;&#160;</a></span>TIM_TIM24_ETR_GPIO</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM24_ETR_GPIO&#160;&#160;&#160;0x00000000U</td>
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      </table>
</div><div class="memdoc">
<p>TIM24_ETR is connected to GPIO </p>

</div>
</div>
<a id="gab59f38eafd161977848d82893351f552" name="gab59f38eafd161977848d82893351f552"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab59f38eafd161977848d82893351f552">&#9670;&#160;</a></span>TIM_TIM24_ETR_SAI1_FSA</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM24_ETR_SAI1_FSA&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga6a1413b9834ebc2b96c8eb27b74b0fdc">TIM2_AF1_ETRSEL_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff3eda56bcb98d020fa1b1573c4f912">TIM8_AF1_ETRSEL_0</a>)</td>
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      </table>
</div><div class="memdoc">
<p>TIM24_ETR is connected to SAI1 FS_A </p>

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</div>
<a id="ga0bf08e73da65956929e36e05e4873c42" name="ga0bf08e73da65956929e36e05e4873c42"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0bf08e73da65956929e36e05e4873c42">&#9670;&#160;</a></span>TIM_TIM24_ETR_SAI1_FSB</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM24_ETR_SAI1_FSB&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga38cf3fbfe20afba58f315ace95c88016">TIM2_AF1_ETRSEL_2</a></td>
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      </table>
</div><div class="memdoc">
<p>TIM24_ETR is connected to SAI1 FS_B </p>

</div>
</div>
<a id="ga02942441fbd3f26678ff95395a09b89c" name="ga02942441fbd3f26678ff95395a09b89c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga02942441fbd3f26678ff95395a09b89c">&#9670;&#160;</a></span>TIM_TIM24_ETR_SAI4_FSA</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM24_ETR_SAI4_FSA&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gabaeb0ecb379e37e51722902144404520">TIM5_AF1_ETRSEL_0</a></td>
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      </table>
</div><div class="memdoc">
<p>TIM24_ETR is connected to SAI4 FS_A </p>

</div>
</div>
<a id="gade1f234256056c4a8739abb2c6e35f26" name="gade1f234256056c4a8739abb2c6e35f26"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gade1f234256056c4a8739abb2c6e35f26">&#9670;&#160;</a></span>TIM_TIM24_ETR_SAI4_FSB</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM24_ETR_SAI4_FSB&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga92b38d638ecda48a0da085cfd8ce86bf">TIM5_AF1_ETRSEL_1</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM24_ETR is connected to SAI4 FS_B </p>

</div>
</div>
<a id="ga79a125bc7559dc01f8de056e19f11972" name="ga79a125bc7559dc01f8de056e19f11972"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga79a125bc7559dc01f8de056e19f11972">&#9670;&#160;</a></span>TIM_TIM2_ETR_COMP1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM2_ETR_COMP1&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gaaa7a4ed17a8432d8c81e31e32dd87e20">TIM2_AF1_ETRSEL_0</a>)</td>
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      </table>
</div><div class="memdoc">
<p>TIM2_ETR is connected to COMP1 OUT </p>

</div>
</div>
<a id="ga76dfe019f143b4bff5ba2c2e1a38a387" name="ga76dfe019f143b4bff5ba2c2e1a38a387"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga76dfe019f143b4bff5ba2c2e1a38a387">&#9670;&#160;</a></span>TIM_TIM2_ETR_COMP2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM2_ETR_COMP2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga6a1413b9834ebc2b96c8eb27b74b0fdc">TIM2_AF1_ETRSEL_1</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM2_ETR is connected to COMP2 OUT </p>

</div>
</div>
<a id="ga05e1c800a3f8e7eb60b50f446cf321f7" name="ga05e1c800a3f8e7eb60b50f446cf321f7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga05e1c800a3f8e7eb60b50f446cf321f7">&#9670;&#160;</a></span>TIM_TIM2_ETR_GPIO</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM2_ETR_GPIO&#160;&#160;&#160;0x00000000U</td>
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      </table>
</div><div class="memdoc">
<p>TIM2_ETR is connected to GPIO </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gae69141882323f8b603da7a0343995dca">&#9670;&#160;</a></span>TIM_TIM2_ETR_RCC_LSE</h2>

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          <td class="memname">#define TIM_TIM2_ETR_RCC_LSE&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga6a1413b9834ebc2b96c8eb27b74b0fdc">TIM2_AF1_ETRSEL_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff3eda56bcb98d020fa1b1573c4f912">TIM8_AF1_ETRSEL_0</a>)</td>
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<p>TIM2_ETR is connected to RCC LSE </p>

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<a id="ga901919d24f481b3ca744ff06cd98bdb8" name="ga901919d24f481b3ca744ff06cd98bdb8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga901919d24f481b3ca744ff06cd98bdb8">&#9670;&#160;</a></span>TIM_TIM2_ETR_SAI1_FSA</h2>

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          <td class="memname">#define TIM_TIM2_ETR_SAI1_FSA&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga38cf3fbfe20afba58f315ace95c88016">TIM2_AF1_ETRSEL_2</a></td>
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<p>TIM2_ETR is connected to SAI1 FS_A </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gab369084ac6b74b818f48995770cf2221">&#9670;&#160;</a></span>TIM_TIM2_ETR_SAI1_FSB</h2>

<div class="memitem">
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          <td class="memname">#define TIM_TIM2_ETR_SAI1_FSB&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga38cf3fbfe20afba58f315ace95c88016">TIM2_AF1_ETRSEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff3eda56bcb98d020fa1b1573c4f912">TIM8_AF1_ETRSEL_0</a>)</td>
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<p>TIM2_ETR is connected to SAI1 FS_B </p>

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<a id="gaea6cbaddf4da816fd4afd13ad7953079" name="gaea6cbaddf4da816fd4afd13ad7953079"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaea6cbaddf4da816fd4afd13ad7953079">&#9670;&#160;</a></span>TIM_TIM3_ETR_COMP1</h2>

<div class="memitem">
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          <td class="memname">#define TIM_TIM3_ETR_COMP1&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaaf25073af3e775f18278b711d3719957">TIM3_AF1_ETRSEL_0</a></td>
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<p>TIM3_ETR is connected to COMP1 OUT </p>

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<a id="gad86579b249d2c04a99c8412a8c72af97" name="gad86579b249d2c04a99c8412a8c72af97"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad86579b249d2c04a99c8412a8c72af97">&#9670;&#160;</a></span>TIM_TIM3_ETR_GPIO</h2>

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          <td class="memname">#define TIM_TIM3_ETR_GPIO&#160;&#160;&#160;0x00000000U</td>
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<p>TIM3_ETR is connected to GPIO </p>

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<a id="ga5df745d19761f4c212140c70d4271692" name="ga5df745d19761f4c212140c70d4271692"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5df745d19761f4c212140c70d4271692">&#9670;&#160;</a></span>TIM_TIM5_ETR_GPIO</h2>

<div class="memitem">
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          <td class="memname">#define TIM_TIM5_ETR_GPIO&#160;&#160;&#160;0x00000000U</td>
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<p>TIM5_ETR is connected to GPIO </p>

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<a id="gaca05dbe7ce7bc979d5e30f355285a51c" name="gaca05dbe7ce7bc979d5e30f355285a51c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaca05dbe7ce7bc979d5e30f355285a51c">&#9670;&#160;</a></span>TIM_TIM5_ETR_SAI2_FSA</h2>

<div class="memitem">
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          <td class="memname">#define TIM_TIM5_ETR_SAI2_FSA&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gabaeb0ecb379e37e51722902144404520">TIM5_AF1_ETRSEL_0</a></td>
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<p>TIM5_ETR is connected to SAI2 FS_A </p>

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<a id="ga11e3c0b2d38048d8d15e8623ff61a408" name="ga11e3c0b2d38048d8d15e8623ff61a408"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga11e3c0b2d38048d8d15e8623ff61a408">&#9670;&#160;</a></span>TIM_TIM5_ETR_SAI2_FSB</h2>

<div class="memitem">
<div class="memproto">
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          <td class="memname">#define TIM_TIM5_ETR_SAI2_FSB&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga92b38d638ecda48a0da085cfd8ce86bf">TIM5_AF1_ETRSEL_1</a></td>
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<p>TIM5_ETR is connected to SAI2 FS_B </p>

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<a id="gac6ad331bf73260161a6e9c3b2ee412f3" name="gac6ad331bf73260161a6e9c3b2ee412f3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac6ad331bf73260161a6e9c3b2ee412f3">&#9670;&#160;</a></span>TIM_TIM5_ETR_SAI4_FSA</h2>

<div class="memitem">
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          <td class="memname">#define TIM_TIM5_ETR_SAI4_FSA&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gabaeb0ecb379e37e51722902144404520">TIM5_AF1_ETRSEL_0</a></td>
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<p>TIM5_ETR is connected to SAI4 FS_A </p>

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<a id="ga5dd267b5ce57d4c9d0736f3da988d9d9" name="ga5dd267b5ce57d4c9d0736f3da988d9d9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5dd267b5ce57d4c9d0736f3da988d9d9">&#9670;&#160;</a></span>TIM_TIM5_ETR_SAI4_FSB</h2>

<div class="memitem">
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          <td class="memname">#define TIM_TIM5_ETR_SAI4_FSB&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga92b38d638ecda48a0da085cfd8ce86bf">TIM5_AF1_ETRSEL_1</a></td>
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<p>TIM5_ETR is connected to SAI4 FS_B </p>

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<a id="ga7a832c5903108f2a06208c58585f7579" name="ga7a832c5903108f2a06208c58585f7579"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7a832c5903108f2a06208c58585f7579">&#9670;&#160;</a></span>TIM_TIM8_ETR_ADC2_AWD1</h2>

<div class="memitem">
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          <td class="memname">#define TIM_TIM8_ETR_ADC2_AWD1&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga8115191f924a8817c45e04078725f242">TIM8_AF1_ETRSEL_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff3eda56bcb98d020fa1b1573c4f912">TIM8_AF1_ETRSEL_0</a>)</td>
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<p>TIM8_ETR is connected to ADC2 AWD1 </p>

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<a id="gae0c7be84fda65b37b00a8896b98775c3" name="gae0c7be84fda65b37b00a8896b98775c3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae0c7be84fda65b37b00a8896b98775c3">&#9670;&#160;</a></span>TIM_TIM8_ETR_ADC2_AWD2</h2>

<div class="memitem">
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          <td class="memname">#define TIM_TIM8_ETR_ADC2_AWD2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga7dc91956b73a05f0ab3465a124e27e97">TIM8_AF1_ETRSEL_2</a>)</td>
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<p>TIM8_ETR is connected to ADC2 AWD2 </p>

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<a id="ga02c57d201dbc0416eed0e333a6347b5b" name="ga02c57d201dbc0416eed0e333a6347b5b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga02c57d201dbc0416eed0e333a6347b5b">&#9670;&#160;</a></span>TIM_TIM8_ETR_ADC2_AWD3</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define TIM_TIM8_ETR_ADC2_AWD3&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga7dc91956b73a05f0ab3465a124e27e97">TIM8_AF1_ETRSEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff3eda56bcb98d020fa1b1573c4f912">TIM8_AF1_ETRSEL_0</a>)</td>
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      </table>
</div><div class="memdoc">
<p>TIM8_ETR is connected to ADC2 AWD3 </p>

</div>
</div>
<a id="ga7cb16632bf98d6961d21172aa42373e3" name="ga7cb16632bf98d6961d21172aa42373e3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7cb16632bf98d6961d21172aa42373e3">&#9670;&#160;</a></span>TIM_TIM8_ETR_ADC3_AWD1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM8_ETR_ADC3_AWD1&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga7dc91956b73a05f0ab3465a124e27e97">TIM8_AF1_ETRSEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga8115191f924a8817c45e04078725f242">TIM8_AF1_ETRSEL_1</a>)</td>
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      </table>
</div><div class="memdoc">
<p>TIM8_ETR is connected to ADC3 AWD1 </p>

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<a id="ga84b90475edbe94a4cdbef6f5f602ac9b" name="ga84b90475edbe94a4cdbef6f5f602ac9b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga84b90475edbe94a4cdbef6f5f602ac9b">&#9670;&#160;</a></span>TIM_TIM8_ETR_ADC3_AWD2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM8_ETR_ADC3_AWD2&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga7dc91956b73a05f0ab3465a124e27e97">TIM8_AF1_ETRSEL_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga8115191f924a8817c45e04078725f242">TIM8_AF1_ETRSEL_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff3eda56bcb98d020fa1b1573c4f912">TIM8_AF1_ETRSEL_0</a>)</td>
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      </table>
</div><div class="memdoc">
<p>TIM8_ETR is connected to ADC3 AWD2 </p>

</div>
</div>
<a id="ga8f39897f883d4efa8357d1ba28bc100b" name="ga8f39897f883d4efa8357d1ba28bc100b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8f39897f883d4efa8357d1ba28bc100b">&#9670;&#160;</a></span>TIM_TIM8_ETR_ADC3_AWD3</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM8_ETR_ADC3_AWD3&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga97fe71b195c1bbc5175e3db42d09c062">TIM8_AF1_ETRSEL_3</a></td>
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      </table>
</div><div class="memdoc">
<p>TIM8_ETR is connected to ADC3 AWD3 </p>

</div>
</div>
<a id="gadcbcb76d19c2ccb5ae46fdc7e7d88f8b" name="gadcbcb76d19c2ccb5ae46fdc7e7d88f8b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadcbcb76d19c2ccb5ae46fdc7e7d88f8b">&#9670;&#160;</a></span>TIM_TIM8_ETR_COMP1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TIM8_ETR_COMP1&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga0ff3eda56bcb98d020fa1b1573c4f912">TIM8_AF1_ETRSEL_0</a></td>
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      </table>
</div><div class="memdoc">
<p>TIM8_ETR is connected to COMP1 OUT </p>

</div>
</div>
<a id="gae93f8a76facb81f8d962bb7c88dc25f0" name="gae93f8a76facb81f8d962bb7c88dc25f0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gae93f8a76facb81f8d962bb7c88dc25f0">&#9670;&#160;</a></span>TIM_TIM8_ETR_COMP2</h2>

<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define TIM_TIM8_ETR_COMP2&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga8115191f924a8817c45e04078725f242">TIM8_AF1_ETRSEL_1</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>TIM8_ETR is connected to COMP2 OUT </p>

</div>
</div>
<a id="gabcec3c5e9dad306b68d34e5b9257a281" name="gabcec3c5e9dad306b68d34e5b9257a281"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gabcec3c5e9dad306b68d34e5b9257a281">&#9670;&#160;</a></span>TIM_TIM8_ETR_GPIO</h2>

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          <td class="memname">#define TIM_TIM8_ETR_GPIO&#160;&#160;&#160;0x00000000U</td>
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</div><div class="memdoc">
<p>TIM8_ETR is connected to GPIO </p>

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